1. Field of the Invention
The present invention relates to the testing of random access memory (RAM) for defects. More particularly, this invention relates to verification of the accuracy of a random access memory built-in self test (RAM BIST) controller.
2. The Prior Art
RAM chips are widely used in various electronic components, most notably computers. The design and manufacture of these RAM chips, however, are not always perfect, opening the door for various types of defects. Defects may also arise during the lifetime of these chips. A defect in a RAM chip could cause serious problems, which include, among other things, the loss of important data and loss of computer function.
Due to concerns about RAM defects, many RAM chips now include a RAM BIST controller, sometimes called a RAM test controller, which tests for defects in the RAM. Normally, when in use in a computer, this RAM BIST controller will run tests on the RAM when the computer is powered up, and stop the operating system from loading if any defects in the RAM are found. Those skilled in the relevant art, however, will recognize that a RAM BIST controller could be used at any time during the life of the chip to test for defects, not just during power up, and it could be used by other electronic components as well, not just computers.
A RAM BIST controller generally operates by performing a RAM BIST, which involves writing patterns into the memory and reading them back for comparison. If a mismatch occurs between the pattern written in and the pattern read back, a defect is usually present in the memory. Currently, most RAM BIST controllers perform some variation of March test algorithm in testing for defects in the RAM. March tests include several March elements, each element comprising a sequence of read/write operations performed on one address. After all of these operations are completed, the same operations are repeated for the next address in either increasing or decreasing order. March tests are very effective for detecting stuck-at, stuck-open, transition, coupling, and data retention faults in the memory.
Despite these advantages, RAM BIST controllers have one major drawback: they are hardwired to the chip itself. Therefore, the determination of which testing algorithm is going to be used must be made when the RAM chip is being designed. The choice of which algorithm to use is a very important process since the choice made will eventually affect the ability of the RAM chip to detect faults in its own memory.
In order to aid in this selection process, different techniques of verifying the logic implementation of these RAM test algorithms have been attempted. One technique is to use a standard memory VHDL model with module testbench. However, since these standard modules are fault-free, they are unable to accurately test how the algorithm will perform in "real life" situations. They work by running the RAM BIST controller model on a model of how the RAM is supposed to perform. The major drawback of this method is that, in most cases, RAM is always "expected" to perform perfectly as that is how it is designed, yet "real world" problems seem to occur during the manufacture and use of the chips that can cause the RAM to perform in ways not expected. Without seeing how the RAM BIST controller would perform in a "real world" situation, a computer model of the RAM BIST controller is virtually useless. Another technique is to use a netlist fault simulation with specific tools. This test, however, has the disadvantage of having to be performed late in the design process, when design is near completion. A second disadvantage of the netlist fault simulation technique is that its run time is very long.
What is needed is a fast and accurate method of verifying the RAM test algorithm that can be implemented throughout the design stage to insure that the RAM chip design is rendered correctly the first time.